Solving America’s Chip Manufacturing Crisis

In the previous issue of American Affairs, we argued that the demise of leading-edge chip manufacturing in the United States has created an acute defense industrial base crisis with major geopolitical implications. Recently departed Intel CEO Pat Gelsinger has characterized the former U.S. chip manufacturing champion’s problems as resulting from a fundamental qualitative shift in the economics of leading-edge chip manufacturing for which Intel—and U.S. national security interests—were unprepared. We agree with his diagnosis and will elaborate on it, before proposing measures to address the current defense industrial crisis.

The essence of the current problem was captured in Intel’s 2024 internal production structure. Intel was unable to manufacture its most complex advanced chip products on internal Intel fabrication lines; it instead had to send them off to Taiwan for fabrication by what is effectively a sole-source firm for leading edge silicon, Taiwan Semiconductor Manufacturing Corporation (TSMC). In June 2023, some 20 to 25 percent of the silicon packaged in Intel chips was fabricated externally.¹ A year ago, in April 2024, that share had risen to roughly 30 percent.²

Intel long integrated chip fabrication with chip design but began moving away from that model, with a unit for design and a unit for chip fabrication: the split of fabrication without design is known as a “foundry” model and was pioneered by TSMC. Intel’s most advanced chip designers in its newly formed Intel Products unit now practically function as a fabless chip design house. Intel Products was essentially funding a competitor to Intel Foundry, its new chip fabrication unit, when it paid high TSMC profit margins on the leading-edge silicon used in 100 percent of its most advanced processor, GPU, and AI accelerator chips. The same alarming degree of dependence on a sole Taiwanese source for all leading-edge chips is also evident at other U.S. electronic system design businesses, namely leading tech firms like Nvidia, Qualcomm, AMD, Apple, Google, Amazon, and Meta.

The political and business risks arising from a sole source of supply (as described in our last article) have become evident to the largest customers for these chips, and they are now considering efforts of their own to establish second sources in a somewhat less risky location. Nvidia and Qualcomm (respectively, the number one and two U.S. fabless chip designers in terms of sales, at $61 and $39 billion in 2024 revenues) were reportedly considering shifting a significant portion of their 2 nanometer chip designs from TSMC to Samsung Foundry, despite issues earlier this year with wafer fabrication yields (which translate into higher cost per non-defective chip).³

A clear-eyed business assessment, it seems, recognizes that having more than a single monopoly supplier is a supply-chain characteristic worth paying for. The willingness of the very largest chip customers to invest in what is effectively a public good is notable. A more competitive and geographically diversified industrial structure, producing lower prices and less interruptible supplies for chip users, can be framed as a type of public good, since other “free rider” advanced chip customers will also benefit economically from cheaper chip prices with less likelihood of costly political-military interruption. As with other public goods (like national security), economic logic supports a role for government in ensuring enough geographical and industrial diversification is provided. This leads us to a discussion of chip fabrication economics.

The Changing Economics of Chip Manufacturing

Economies of scale are the fundamental economic force reshaping industrial structure in leading-edge chip fabrication. For context, note that at the peak of its market power in the global computer processor (CPU) market in the third quarter of 2014, Intel alone produced a record 100 million x86 processors (x86 is Intel’s famous foundational architecture and instruction set for computer processors), implying an annual Intel production rate of somewhere between 300 and 400 million processors.⁴ Using that era’s leading-edge manufacturing technology, the production of that many processors filled multiple Intel fabs.⁵

Post-Covid sales of all x86 processors, however, including chips sold by both Intel and its competitor Advanced Micro Devices (AMD), dropped to roughly the 60 to 70 million range per quarter in 2022 and 2023, or around 240 to 280 million a year.⁶ This was due to a number of causes: a slowdown in Moore’s Law–driven processor price declines, resulting in longer x86 PC service lives and diminishing replacement demand; Apple replacing its x86 Intel processors with its internally developed Macintosh computer processor designs (in 2020); and adaptation by Microsoft of its Windows operating system code to use ARM processors. Since AMD had a rising share of the x86 market, this represents a drop in Intel processor volumes of perhaps 30 to 50 percent from its peak a decade before.⁷

Intel’s economic pain from this reduced demand for its core chip product, x86 processors, was amplified by substantial increases in the minimum efficient scale for volume production at recent technology nodes. This, coupled with soaring costs for cutting-edge Extreme Ultra Violet (EUV)–based fabrication lines, is the qualitative shift in the economics of leading-edge chip fabrication referenced in Gelsinger’s April 2024 analysis, cited in our last article.

Hard numbers on foundry manufacturing economics are scarce, but TSMC’s public presentations emphasize a large role for scale economies in lowering unit manufacturing costs. These scale economies are driven by the fixed costs of very expensive capital equipment, like EUV patterning equipment, and amortizing its cost over the lifetime of a fab. Typically, fabs run around the clock to squeeze maximum output from these costly fixed capital investments.

When, inevitably, an EUV machine goes offline for maintenance or repair, production throughput declines, unless there is spare underutilized capacity to fill the gap. The costs of maintaining spare capacity to fill in for both random equipment failures and scheduled interruptions to production is going to be lower, as a percentage share of investment requirements, for a very large capacity fab with many such costly machines, than for a small fab with a handful of the most costly machines, which turn into production bottlenecks in the event of equipment failure.

For very large capacity fabs, the overhead cost of maintaining sufficient spare capacity to offset random equipment failures is a much smaller share of overall fab cost than for very small fabs. Also, so-called learning economies are going to be greater in a large-scale fabrication facility than on a small-scale production line: such economies are synonymously called “learning-by-doing” or “experience curves,” where increases in equipment productivity are derived from accumulated production experience that assists in optimizing manufacturing processes and equipment use.⁸ This is because cumulative experience with processing wafers will be greater on the higher throughput fabrication line.

Since wafer processing experience occurs at the fab line level, both Intel and TSMC have long had some version of a “copy exactly” strategy. This means that if multiple fabs are producing at a particular technology node, the firm ramps up the process at one fab until higher yields of non-defective chips per wafer are achieved, then it copies the successful line (both equipment configurations and processing steps) exactly in order to maximize company-wide yields of good, non-defective chips per processed wafer.

With larger-scale fabs, cycle times (the time from wafer start to finished wafer) will also be lower, fab throughput (successfully processed wafers per month) higher, and processing cost per wafer (including amortization and depreciation cost on the fixed plant and equipment) per unit lower. These elements represent the well-understood techniques and benefits of mass production.⁹

It is worth listening to what TSMC, the largest-scale logic chip manufacturer in the world today, has to say about the relationship between scale and the cost of manufacturing logic chips. TSMC has long classified its fabs by production capacity: “mini-fabs,” with a capacity of roughly ten thousand 300 millimeter (12 inch) diameter silicon wafer “starts” per month; “mega-fabs” with roughly twenty-five thousand wafer starts per month capacity; and “giga-fabs,” with capacities to process over one hundred thousand wafer starts per month.¹⁰ TSMC currently operates four such giga-fabs, all in Taiwan, which process wafers using a mix of technology nodes ranging from 130 to 3 nanometers.¹¹ Driven by rising costs for more expensive equipment sets in current generation fabs, the TSMC definition of a giga-fab has been upsized over recent decades, from eighty thousand wafer starts per month back in 2006, to over one hundred thousand wafer starts per month in the EUV era.¹²

TSMC characterizes operating costs at giga-fabs as being “low” versus “high” at mini-fabs, flexibility as being “high” in giga-fabs, versus “limited” in mini-fabs, and cycle time as “short” in giga-fabs versus “long” in mini-fabs. Similar contrasts are drawn for “ramp-up agility” (presumably meaning the ability to apply experience curve learnings quickly to process and equipment adjustments) and on-time “delivery precision.” Mega-fabs are characterized as uniformly “medium” on all these metrics.¹³

Memory chips—both flash memory and DRAM, the largest volume “commodity” products produced by the semiconductor industry—have long been produced in what would be classified as giga-fabs by the handful of remaining memory producers. As is true for logic chips, the scale (in wafer starts per month) of memory chip giga-fabs has also been increasing at recent, more costly technology nodes.

This increase over recent decades in the minimum efficient scale (where low average production costs are achieved) for a leading-edge fabrication facility is directly related to the increasing concentration visible in fabrication of both leading-edge logic chips and leading-edge memory chips. In addition, the soaring fixed R&D investment requirements demanded for chip design at recent technology nodes have meant that use of the most advanced technology nodes has only been economically feasible for fabless design groups with applications likely to be produced in relatively high volumes.¹⁴

Last Man Standing

Intel is one of the last survivors, in logic and system chips, of what used to be the dominant species in the semiconductor manufacturing ecosystem: the integrated device manufacturer (IDM). IDMs do both the design and the manufacturing of the chips they sell. The economic argument for being a successful IDM was that if you had a good product, allowing you to seize a large share of the market, you could afford to optimize manufacturing processes for your design. Optimization entailed using the most advanced available technology node, which in turn lowered costs and increased profit margins. As part of a virtuous cycle, more advanced technology nodes also delivered rapidly declining transistor costs, enabling more sophisticated chip designs that delivered higher performance for less expense, thus locking in large market shares and high volumes.

That environment gradually disappeared over the last twenty years. As the price tag for a high volume, low cost giga-fab at the most advanced technology node soared to astronomical levels (currently $20-30 billion), IDMs with smaller market shares ceased to be IDMs. Or they became instead specialized IDMs, using fabrication processes tuned to niche designs and markets where use of the most advanced technology node with the smallest feature sizes conferred little or no technical or economic advantage.

The largest U.S. IDMs of the 1970s and early 1980s, Texas Instruments and Motorola, took the specialized IDM route as the semiconductor world changed in the twenty-first century. Texas Instruments became a specialized IDM for analog, linear, and signal processing chips, and a fabless design house for leading-edge logic and system chips. Motorola exited the semiconductor business in 2003 entirely, spinning off its semiconductor operations into a specialized IDM, Freescale, which focused on automotive, industrial, and communications markets (it merged in 2015 with another specialized IDM, NXP, which was in turn descended from the older IDM, Philips).

Intel has been the sole de facto U.S. national champion in leading-edge logic chip manufacturing since 2010. Its domestic x86 rival, AMD, went fabless in 2008 after having sold off its chip manufacturing business to the Abu Dhabi government, which created the firm Global Foundries from it. IBM divested its microelectronics operations to Global Found­ries in 2015.¹⁵ Global Foundries’ most advanced logic technology node remained at a 12 nanometer process (comparable to other foundries’ 10 nanometer processes). It retains two fabs in the United States (and others in Germany and Singapore) but has dropped out of the market for the most advanced logic chips.

The other remaining U.S. chip-making IDM, Micron, makes memory chips (DRAM and flash) and focuses on design and new product niches, such as mobile and high bandwidth memory. So, it is not a participant in the advanced logic chips contest. Other large U.S. chip firms (i.e., Qualcomm, Nvidia, AMD) are fabless, use foundry firms like TSMC or Global Foundries to make their chips, and base their business strategies on superior designs. Thus, if the Department of Defense (DoD) needs access to a U.S.-based manufacturer of advanced logic chips, there is nowhere else to turn other than Intel Foundry.¹⁶

Intel’s current problems are in part linked to the relentless increase in fabrication equipment costs at every new technology node as well as to the increasing volume of production needed to reach minimum efficient scale at the new nodes. In 2014, Intel’s dominant market position gave it massive volume that was produced at multiple Intel fabs (using the “copy exactly” strategy Intel invented in the 1980s). But by 2023, Intel’s annual x86 processor volumes appear to have dropped 30–50 percent, to 190–230 million sold annually.

Even more important were new processor architectures developed by ARM (a UK firm founded in 1990), which are now used in a wide variety of products—from mobile phones, tablets, Chromebooks, and even PCs; to RISC processors from system companies produced by foundries; to new processor designs and AI chips developed internally by former Intel customers like Google, Amazon, Microsoft, and Meta. These products began displacing Intel chips and amplified a general shift toward mobile computing systems less tethered to the Intel x86 processor architecture (which had not originally been developed with power efficiency in mind).

In 2014, Intel needed to distribute its processor production across multiple leading-edge fabs. By 2023, Intel would have had problems filling a single cost-efficient leading-edge giga-fab with its diminished processor volumes.¹⁷ (A 100,000-wafers-per-month giga-fab might be chunking out roughly 262 million processors annually, compared with actual Intel processor sales of perhaps 190 to 230 million. ¹⁸) Intel now desperately needed additional chip products that could be big hits in the marketplace, with volumes of hundreds of millions of units, in order to justify investments in an efficient, low cost, leading-edge giga-fab for purely internal use.

Intel’s Big Misses

Conceptually, it is possible to visualize scenarios in which Intel could have entered 2023 with sales of new products in volumes that could have filled that giga-fab. Gelsinger, in a November 2023 video interview, supported this position when he gave his analysis of Intel’s three “Big Misses” in recent years¹⁹: missing the “mobile wave,” “fumbling AI,” and an internal Intel bias against taking steps needed to create a “great foundry.”²⁰

The first two of Gelsinger’s misses—mobile device processors and AI chips—are applications that could clearly have joined with mainstream computing processors to fill an Intel logic giga-fab in 2023. Such a development could have prolonged its status as the last remaining “traditional” logic chip IDM. (Memory chips are also used in mobile devices and AI accelerators, so memory volumes have continued to grow at high rates. Divided among the small number of remaining memory chip producers, sales volumes are still large enough to support the memory chip IDMs’ giga-fabs.)

The story of how Intel missed mobile (by rejecting Apple’s request that it develop a new kind of chip for its new iPhone²¹) is now often retold; less so its fumbling of the AI opportunity (by cancelling an AI chip project Gelsinger led, leading him to quit Intel for the first time).²² Both stories are about strategic errors committed by Intel’s top management and board of directors over the decade and a half in which Intel was managed by CEOs less focused on technological advances.

But there were even earlier signals of problems. We would argue that, in the early 2000s, Intel began to stray from the vision of its legendary early leaders Robert Noyce, Gordon Moore, and Andy Grove, who focused on fielding the most technically advanced, complex, and capable products on the market. In the 1980s and early 1990s, under Andy Grove as CEO, Craig Barrett, a former Stanford professor with a technical background, successfully led the resurgence of Intel in chip manufacturing, recapturing a leading position in chip fabrication tech­nology. Barrett spearheaded Intel’s “copy exactly” fab strategy.²³ But after Barrett had moved into the CEO position in the mid-1990s, Intel missed out on being first with an important processor design innovation: the move from a 32-bit architecture to a 64-bit architecture. Intel’s x86 competitor AMD had been the first to define and market a 64-bit extension of the x86 architecture. AMD initially gained significant market share with new 64-bit processors that sold well against Intel’s 32‑bit products.

Intel had also misfired technically during this period by pursuing an x86 architectural alternative (the Pentium 4 “Netburst” architecture) that relied on steadily increasing clock rates (the operating frequency at which a processor performs computations) to improve performance. Simply increasing clock rates could not be maintained for long stretches, due to thermal (heat dissipation) limitations on running ever denser (transistors per area of silicon) processors at ever faster speeds. Intel was ultimately forced to abandon the Pentium 4 architecture around 2006, when Intel released its first processor using its Core architecture—utilizing multiple CPUs (cores) on a single chip, and therefore executing more instructions per clock, at a lower clock rate than Netburst.

The budding success of AMD, capitalizing on its lead in 64-bit processors in the early 2000s, prompted Barrett, and his successor, Paul Otellini, to counterattack. Since superior products were not immediately available, they opted instead for a program of massive financial rebates to personal computer makers intended to reward them for using Intel processors exclusively in their mainstream products and limiting the use of AMD processors to a small share of their shipments. This costly attempt to create and defend monopoly power through an intricately constructed system of rebates and financial initiatives, rather than simply shipping better products, ultimately attracted the attention of antitrust regulators in the United States and the European Union, as well as a private antitrust lawsuit from AMD.²⁴ Intel was found guilty by the EU and fined a billion euros. The large EU fine was ultimately annulled in 2024, but the case continued with battles over a smaller fine. AMD and New York State antitrust suits were settled (in 2009 and 2012, respectively), with AMD receiving $1.25 billion from Intel.

The connection to Intel’s current woes is that the first decade of the twenty-first century was a distracting one for Intel management. The firm’s resources and managerial attention were diverted into sales and marketing initiatives aimed at defending an entrenched position of market power. The company had lost its singular focus on technical innovation that had been its hallmark under Noyce, Moore, and Grove’s early vision for Intel.

The story behind Gelsinger’s third “miss,” its failure to build a “great foundry,” was no less reflective of the firm’s gradual slide into a culture of unfocused diversification. In 2013, Intel made its first venture into offering custom foundry services to external customers using its 14 nanometer process. A small number of customers responded with orders, but costs were high and spread over a small volume. In the face of continuing delays in introducing its follow-on 10 nanometer technology, Intel management shut down the effort in 2018.²⁵

The latest attempt by Intel to create a “great foundry” has had trouble getting off the ground since it was launched in 2021. Intel’s new “IDM 2.0” approach was announced by Gelsinger in 2021, but Intel, even though it now has a foundry unit, remained a device designer as well as a maker. Potential customers have understandable fears that an Intel foundry might prioritize Intel-designed wafers over their own in scheduling wafer starts. Potential clients also have fears that information about their wafer fabrication orders, if available to top Intel management, might provide Intel with valuable strategic information about their success or failure in manufacturing and marketing new products, useful in making decisions about launching competitive Intel designs. Sharing intellectual property is also an issue. Potential customers might reasonably fear that Intel would gain insights from troubleshooting their designs’ manufacturing issues and use those insights to compete against them.

The internal “bias against a great foundry” probably also included Intel’s own internal chip design mentality. The firm struggled with requests for special treatment or special cost chargebacks for wafers originating in high priority internal design projects. Intel manufacturing practice tended to view chip fabrication as a captive service arm centered on Intel’s own internal design group priorities.²⁶

In contrast, under TSMC’s foundry model, its customers use TSMC’s Process Development Kit (PDK) at their own cost and risk, and TSMC stays completely out of the design business. In 2024, in an attempt to deal with this problem, Intel began the separation of its design business (Intel Products) from its newly stood-up Intel Foundry. The latter was slated to become an independent subsidiary with substantial autonomy, complete with its own board, bylaws, and operating structure. This action was intended to provide foundry services for chip design firms with stronger protection for both their intellectual property and sensitive business information.

Intel also announced at the same time a major new foundry customer: Amazon Web Services, the leading cloud computing provider, which is set to use Intel Foundry to manufacture chips, including customized server devices (a multi-billion-dollar arrangement). While these steps mark progress for Intel, it has not yet reached the bottom line.

Intel may need to go a step further and spin off Intel Foundry and Intel Products into separate corporations, to address the needs of external foundry customers for reassurance about their priority in allocating manufacturing resources, and the security of their information—both IP and strategic business information related to products and order volumes. Intel Foundry and Intel Products should be entities with a legal obligation to deal with each other at arm’s length, if both companies are to succeed. Nevertheless, it is difficult to spin off Intel Foundry, with its massive inventory of production fabs and associated workforce, without a secure and substantial customer base outside Intel, something that has yet to materialize.

Former Intel CEO Barrett has argued against the full separation, suggesting that if Intel can again offer the best chips, customers will put aside some of their separation concerns.²⁷ Some argue there are also potential gains that would be lost in a split, in “design for manufacturing” capability and in production cost, speed, and quality from more integrated operations.²⁸ These were effectively the same arguments made for the IDM model during its heyday.

The verdict of economic history appears to have been delivered already, however. The choice between cost benefits from aggregating multiple customers (to reap gains from steadily increasing economies of scale in ever more costly leading-edge fabs) versus gains from the internal optimization of fabrication processes (to reduce costs for a single chip designer’s proprietary designs) has by now become clear. The weight of the numbers shows that the economic winner is cost-effective fabrication of many different logic chip designs using standardized fabrication processes in a giga-scale foundry. Requiring customers to drop their concerns over handing over IP and manufacturing information to a potential competitor also puts Intel Foundry at a competitive disadvantage. Remaining financial connections, however, between Intel Foundry and Intel Products are likely create complex short-term transition issues.

It should be emphasized that Intel Products, by necessity, has already begun to function as a fabless design company in many respects. The 30 percent of Intel wafers being fabricated externally in 2024 required Intel designers to use industry-standard design tools and formats as well as standardized PDKs from TSMC and other foundries, rather than proprietary internal Intel design processes. Intel likely needs to go the last mile and make Intel Products and Intel Foundry entirely separate entities that deal with one another at arm’s length in order to solve its transition problem, once it achieves a scale-up of its 18A production. This logic is quite different from Wall Street pressure to boost short-term investor returns by breaking up Intel and selling off its pieces (including possibly to TSMC).²⁹ The standard Wall Street “chop it up” stratagem would leave the defense chip industrial base problem unsolved, while exacerbating the potential chip manufacturing monopoly problem faced by U.S. chip designers.³⁰

Intel Foundry is currently the less technologically challenged of the two Intel units. It seems to be on the cusp of delivering a leading-edge volume chip manufacturing technology (its 18A process) at scale. Intel’s use of the most advanced available chip patterning technology (high numerical aperture EUV lithography) and its first-to-market introduction of backside power delivery (which TSMC has not yet implemented) in its new manufacturing processes could deliver Intel Foundry a substantive competitive advantage. Yet it still faces the economic challenge of finding enough foundry customers to reach a cost-efficient scale for its manufacturing operations in a capital-intensive business that demands continuing large-scale investments to stay competitive.³¹

As we previously argued, there is no national security rationale for subsidizing Intel Products, which has numerous successful U.S. chip design competitors. Intel Products currently lags multiple U.S. peers in supplying competitive, power-efficient AI, GPU, CPU, and mobile communications designs. Intel Foundry is another matter.

A Commercially Viable Intel Foundry:
A National Security Necessity

With Intel clearly behind in fabricating advanced chips, Pat Gelsinger was brought back to Intel as CEO to rescue the company in 2021.³² He bet big. He embarked on a $100 billion, high-risk strategy to bring Intel back to a leadership position. He knew it would take years, if it could be done. He created the new foundry model within Intel. He pushed for advanced chip development for new 20A and 18A chips, and he poured billions into the construction of four huge new fabs in Ohio and Arizona to make them. He secured $7.8 billion in direct federal assistance for the new fabs, in addition to $11 billion in guaranteed loans and investment tax credits under the chips Act—on top of a further $3 billion from DoD for a “secure enclave” to make DoD chips.³³

Added to this were funding commitments from the EU, customer prepayments for access to Intel’s 18A technology node, and investments in new Intel fab lines from private financial partners, with Intel reportedly accessing over $50 billion in external capital commitments.³⁴ Gelsinger negotiated with ASML, the Netherlands-based maker of advanced EUV lithography equipment, for the first of their next generation of EUV equipment for the new fabs. These were the steps needed to enable an Intel transformation. But the wave of investments left Intel with a near-term capital cost of $16 billion a year. None of this would see returns for years.

Chip markets are often cyclical, and in 2023, after a boom during Covid, the market for CPU chips declined. In August 2024, Intel announced it was laying off seventeen thousand workers (15 percent of its workforce) and stopping all “nonessential work.” It cancelled its 20A chip project to focus on its 18A chip fabrication process. It posted the largest loss in its history in the third quarter of 2024: $16 billion, writing off several losing projects, although its revenue exceeded expectations.³⁵ It subsequently pushed back the schedule for its new plants in Ohio and Arizona. The 18A chipmaking process remains a lynchpin for Intel’s future.³⁶ It is too early to declare 18A a success or failure, but the massive resources already sunk into this strategy—by Intel, its private investment partners and customers, and by the U.S. government—make a certain amount of patience a reasonable ask from both financial markets and the Intel board.

Chip fabrication in a foundry is a capital-intensive business with large scale economies. There are high margins only at leading-edge technology nodes, where there are few competitors and considerable pricing power. TSMC’s uniquely high profitability as a foundry is built on its market power for leading-edge fabrication capability. It is also built on significant subsidies to its large capital investments that are provided by the government of Taiwan.

Chips fabricated in the United States currently account for 12 percent of the global chip market, and the United States currently mass produces none of the most advanced chips. This shift in production capacity out of the United States has been driven in large part by financial support provided by foreign governments to their semiconductor sectors.³⁷ Semiconductors are the most automated manufacturing sector in the world, so labor costs are only a small part of production costs. But capital costs are enormous: the most advanced EUV fabs can now cost $30 billion or more. Given this scale, government financing is key. China, Taiwan, Korea, and Japan all provide major subsidies in various forms, which the U.S. government made no attempt to match prior to the chips Act: as a result, no new leading-edge logic fabs were built in the United States for some thirteen years (until 2024).³⁸

The stakes for U.S. national security in Intel’s survival are high because new kinds of warfare are evolving that will require assured access to the most advanced chips. Artificial intelligence, quantum computing, autonomous drones, and advanced data centers all now demand leading-edge chips to maintain a technological advantage. There is no readily available alternative to making Intel’s transformation plans work. The 18A chip manufacturing process is central to solving this security dilemma, so further patience and support may be needed to ensure its success. The federal government’s investments in Intel to date give it leverage to try to ensure that Gelsinger’s successors make the firm’s transformation work.

Intel Foundry is not really a case of “too big to fail”; it is a case of “too intertwined with national security to fail.” There are no other U.S. company alternatives to Intel Foundry: the capital costs of entering advanced chip manufacturing, R&D, and production are staggering, the technology challenges and risks are massive, and all of Intel’s former U.S. competitors have by now exited advanced chipmaking. The national security imperative requires that the U.S. government backstop Intel Foundry, since that is the only place where assured access to the most advanced chips is going to happen if worst-case security contingencies materialize. In contrast, national security does not require support for Intel Products, which is just one of many U.S. entities with the capability to design leading-edge chips.

The United States has imposed a series of export control regulations in an attempt to block China’s access to advanced chips and the equipment needed to make them. Unfortunately, the history of such controls suggests that they are likely be effective only in the short run, at best, for eventually technology disseminates. In the meantime, China (and Russia) have been making systematic and at least partially successful attempts to get around semiconductor export controls.³⁹ The only real solution to maintaining a defense technology edge is to invest in securing an ongoing position at the outer perimeter of the technological frontier.

And it is hard to see how the United States does this without reinvigorating Intel Foundry capabilities along the lines that Gelsinger was aiming for. Gelsinger’s overall plan showed considerable signs of progress before the Intel board apparently lost patience. (Intel manufacturing went from being two generations behind TSMC when Gelsinger arrived in 2021, to one generation behind in 2024; Intel’s current GPU and AI accelerator product designs are also looking more competitive in the low and mid-range segments of these markets.)

DoD, therefore, may have to think the unthinkable and consider further steps to shore up Intel and wring needed benefits from the capital investments already sunk into Intel’s new chip production lines.⁴⁰ It has already started to move in this direction with an award of up to $3 billion to Intel for a “secure enclave” to produce chips for DoD in a secure domestic supply chain for advanced chips.

Aside from DoD, major U.S. tech companies, like Nvidia, Qualcomm, IBM, Microsoft, Google, Meta, etc., have a critical stake in retaining a major U.S. leading-edge chip fabricator and de-risking their current sole-source Taiwan supply chain for cutting-edge products. They are much better off with a competitive advanced chip market in lieu of a monopoly supplier. As noted above, Amazon has already stepped up to the plate with a long term, potentially multi-billion contract with Intel’s foundry for advanced chips for its cloud computing services. DoD should help assemble a coalition of the willing (of fabless U.S. tech firms, including Intel Products) to commit to contracts and/or take stakes in a spun-off Intel Foundry.

Alternatively, a merger between the currently constituted Intel and another U.S. semiconductor firm might be possible. Trump administration officials have reportedly been in talks with TSMC about purchasing Intel Foundry (possibly in a joint venture with Nvidia, Broadcom, and AMD),⁴¹ but this seems to have met an appropriately cool reception in various circles.⁴² Talks, however, have been held between CEOs of the two firms. Absorbing the only U.S. leading-edge chip fabrication alternative into TSMC would lock TSMC’s monopoly power in place, while doing little to ensure that future advanced R&D and production capability would remain available onshore. Likewise, acquisition of Intel Foundry by another U.S. semiconductor producer that did not guarantee support for future R&D and capital investment would do nothing to address the ongoing defense industrial crisis.

If the government intervened, this would not be the first time the United States has acted to sustain critically positioned firms.⁴³ Federal bailouts began in 1792 when the first secretary of the treasury, Alexander Hamilton, authorized securities purchases to avoid a crash.⁴⁴ More recently, during the 1979 energy crisis, Congress, with the support of the Carter administration, stepped in to support Chrysler.⁴⁵ In 2008, to avoid a second Great Depression, the Bush administration provided $426 billion to major financial firms through its “Troubled Assets Relief Program.” Some $17 billion was additionally provided by President Bush to salvage bankrupt U.S. automakers in the same period. Under a Capital Purchase Program, the federal government acquired $205 billion in shares of financial firms, so they could continue to provide liquidity during this crisis. These efforts were not politically popular—many resented the “too big to fail” doctrine behind them. But they were likely crucial to a recovery, providing “bridge” financing with virtually all of it repaid over time.⁴⁶ Intel is not operating in a fading industry destined for decline: leading-edge semiconductor producers are assured of an expanding market for the foreseeable future.

And this is not simply a subsidy story. From an economic perspective, entry (or in Intel’s case, reentry) by another leading-edge chipmaker in addition to TSMC creates externalities (increased competition and innovation, producing better products at lower prices benefiting U.S. chip users, economic benefits not fully captured by the entrant) that justify a subsidy to entry (i.e., an industrial policy) on economic grounds.⁴⁷

In parallel to Intel Foundry support, the United States also needs to engage in a much-needed dialogue with Taiwan and TSMC. In the first Trump administration, Commerce and State Department officials insisted that TSMC locate plants in the United States, so this is not a new idea.⁴⁸ TSMC should only receive continued federal support if it commits to U.S.-located “mirrors” for leading edge process development and production fabrication capabilities undertaken in Taiwan.

A similar dialogue may not be needed with Samsung. Samsung is reportedly developing cutting-edge technology in its subsidized U.S. facilities,⁴⁹ while TSMC is not (among other reasons, perhaps, because of Taiwan’s “Silicon Shield” tech hostage laws).⁵⁰ This needs to change.

Back to the Future

On February 13, 2025, President Trump announced his intention to impose a 25 percent tariff on U.S. semiconductor imports. He allowed a temporary reprieve,⁵¹ but tariffs still hit U.S. semiconductor equipment makers.⁵² Tariffs would create enormous short-term economic shocks for chip-consuming electronic equipment industries located in the United States: one supply-chain analysis firm estimated that of about 2.9 million semiconductor parts used by U.S. electronic equipment producers, only about 4 percent had U.S. country of origin availability.⁵³ Creating new semiconductor fabs in the United States to replace more costly imports would take many years, not months, if it were to happen. The more interesting question is whether the short-term economic pain inflicted on chip-using, U.S.-located electronic equipment manufacturers would be offset by long-term economic gain via chip suppliers relocating manufacturing operations to the United States to avoid these tariffs.

On this question, little speculation is required. The European Community (EC) imposed a steep 17 percent tariff on semiconductors in the 1960s, which continued through the 1970s and 1980s. Tariffs on electronic circuit boards (containing chips) and electronic equipment (containing circuit boards) were much lower, creating a considerable incentive for electronic equipment manufacturers to move their manufacturing operations offshore to gain access to less expensive semiconductor inputs. That is precisely what happened.

At the same time, leading-edge chip producers (then a sea of American faces) set up subsidiaries in Europe to supply European electronic equipment manufacturers selling into a protected European market. Some of these were chip fabrication plants, but more were assembly and test facilities importing foreign-made silicon and completing the finished chips in a European location.⁵⁴ By the mid-1970s, the net result was a European market where chips were priced substantially above U.S. and Japanese levels.⁵⁵ Unsurprisingly, the European share of sales in global markets for these components dropped sharply as European prices increased.⁵⁶

Starting in the late 1970s, struggling European computer and electronics producers began asking national authorities to suspend chip tariffs on a case-by-case basis, to allow them to produce their products at a cost-competitive level with imports, and to make them more viable in global export markets. Use of these tariff suspensions became so widespread that the average collected duty on imported semiconductors in the EC fell by two-thirds, to 5 to 6 percent.⁵⁷

Thus, European chip tariffs ultimately strengthened the power of administrative state functionaries considerably, as they struggled to reduce negative long-term economic policy fallout from a tariff-centered industrial policy. These trade policies did little, however, to improve the competitive fortunes of European electronic equipment producers, and the European computer industry—a “strategic sector” from a European defense industrial perspective—continued its long-term decline.

European governments had better luck with large-scale national technology investments. In the 1980s, Dutch electronics producer Philips and German producer Siemens participated in a billion-dollar semiconductor technology “Megaproject,” one-third funded by their national governments, that led to Siemens successfully entering the memory chip (DRAM) business. Siemens’s DRAM-producing subsidiary (Infineon, later spun off into Qimonda) was a major player in global markets. After 2008, when the economic fallout from the global financial crisis triggered a major global consolidation and restructuring in the DRAM business, both Qimonda and many of its Taiwanese DRAM manufacturing partners ended up shutting down.

Philips chose to invest in technology to produce another type of memory (SRAM, which was still in the process of being incorporated into large-scale logic chips, like CPUs), and never commercialized this business. It sold its fabrication technology and intellectual property—including the production line it had set up to manufacture these chips—to a (then) little-known Taiwanese start-up named TSMC, in exchange for cash and a substantial equity share, an asset Philips held until cashing out in 2008.

In short, tariffs have a poor track record as an industrial policy tool in critical technology sectors like semiconductors that are highly globalized. If this misguided policy were to be actively pursued in the United States, we would expect U.S. electronic equipment producers to migrate offshore. If this, in turn, stimulated the imposition of U.S. tariffs on electronic capital goods, we would expect capital-intensive electronic service industries—like IT cloud services—to exit the U.S. for offshore locations, to reduce their cost disadvantage. None of this would be good for the U.S. defense industrial base.

It is important to always remember that high-technology industry is, by its very nature (huge fixed investments in R&D), highly dependent on reaping economies of scale by attracting customers in the largest possible market in order to reduce unit costs. Success in high tech means selling to foreign friends and allies, who can be expected to demand reciprocal access to the U.S. market for their products. Constructing a new U.S. cost disadvantage will not help the U.S. semiconductor and electronics industries.

Steering Intel Foundry onto a path of commercial success is only part of the story. National security goals will only be met if DoD is able to access a viable leading-edge semiconductor manufacturing capability in the future as well. It is economically and technically impossible for DoD to create its own captive leading-edge chip contractors. Defense is far too small a customer to use its purchases to sustain the scale of investment needed for both R&D and future production facilities—or to stay at the technology frontier as it continues shifting forward. And this is a long game. The chips Act authorization runs out in 2027; steps beyond that need to be considered now along with a sustained R&D effort.

Financial Support for Future
Semiconductor Manufacturing Capability

In addition to the task of supporting Intel Foundry’s commercial success, there is a longer-term financing task.⁵⁸ The chips Act is a stop­gap measure. It assures some production in the United States of the pending generation of advanced chip processes, but not the following generations of chips.⁵⁹ It was a onetime law with the authorization running out, as noted, in 2027; and the funding for new fab construction is already committed. The U.S. semiconductor challenge is a long-term one, and CHIPS was an important but decidedly short-term fix.

What will happen when the industry moves to the next chip generation? U.S. fab costs are higher for private investors than in other producer nations, primarily because of government subsidies, and to stay in the game, the United States will have to match those subsidies on an ongoing basis. The U.S. will need more chips Acts over a longer timeframe. Yet it is by no means assured that there will be such a program, for President Trump has repeatedly criticized the chips Act and called for its repeal.⁶⁰ Aside from the financing provisions, there are also important R&D provisions in the chips Act, which aim to establish the groundwork for ongoing technology advances in semiconductors. While initial funding for this is strong, it too will require reauthorization and future funding.

Where does this leave DoD? The programs set up by the chips Act chiefly reside in the Commerce Department and its National Institute for Standards and Technology (NIST), not in DoD. Historically, DoD had always been the leading government actor on semiconductor technology development and policy since the initial invention of the transistor and early days of integrated circuits. But now, except for some modest carve-outs, Congress has given that responsibility to Commerce. DoD, however, retains plenty of authority to undertake future interventions, and with its pressing national security responsibilities and Commerce’s recent entry, it needs to define a new approach to its own role.

If DoD is to adequately secure future access to a supply chain for leading-edge semiconductor chips, it should contemplate the long-term financing stream needed to subsidize continuing research and development as well as production of the latest technology nodes by U.S.-located commercial foundry companies. Given massive continuing subsidies by foreign governments for chip production, the differential between the United States and competitor nations in chip production costs will not disappear after 2 nanometer production is achieved. For DoD to have assured access to the most advanced chips, competitive financing for chip production facilities will continue to be required into the future, post–chips Act. If the chips Act financing is not renewed or replaced, what can DoD do?

While the provisions for $39 billion in grants were the most controversial part of the chips Act, it also provided loan guarantees and investment tax credits for new semiconductor facilities and equipment. The most straightforward solution would be for Congress to beef up these two less controversial financing features. DoD, as a chip customer, makes up less than 1 percent of the total chip market. It is also a low-volume user of customized chips, the opposite of the high-volume standardized chip demands that dominate the commercial chip market. DoD, therefore, lacks market leverage, and a continued government financing role is necessary.

Even if an extension of the loan guarantee and tax incentives does not occur, or if that funding is inadequate, DoD has other potential tools available. It has a new Office of Strategic Capital with loan guarantee authority to help assure DoD access to critical technologies. While still in a pilot stage,⁶¹ it represents a potential funding source to support needed investments in defense industrial base capabilities that should be supported and strengthened.

The Defense Production Act (DPA) has also been used to finance technology projects to address DoD industrial base requirements.⁶² The DPA permits co-funding investment in industrial technology and production capacity for dual-use goods (with both defense and commercial application), within the framework of Defense procurement contracts. DoD has also used government-owned and company-operated (GOCO) authority to create partnerships to partially fund facilities that address government industrial needs. Unless the chips Act is renewed, Congress needs to begin creating budgetary lines for the application of these and other DoD authorities, so that alternative approaches are ready when the next generation of leading-edge U.S. fabs are needed in three to five years.

AI-Driven Design Initiatives

Because the chips Act is predominately targeting near-term chip technology development needs, and since it may ultimately only be a five-year program, there is an opportunity for DoD to actively support longer-term projects with major national security synergies. At the very top of that list is the application of AI to chip design.⁶³

The specialized, targeted accelerator chip designs increasingly used for machine learning and AI confirm that an era of more customized chips is already upon us. Yet dramatically soaring costs for chip design for application-specific ICs (ASICs) manufactured using leading-edge technology are currently a very high barrier to more generalized industrial use of the most integrated, customized chips. Staggeringly high fixed design costs mean that it makes no economic sense to use leading-edge manufacturing technology on chip designs that (at least initially) will ship only in low to moderate volumes, unless the application places a huge premium on power efficiency or reduced size that justifies a high unit cost.

DoD faces a similar problem: technological superiority in military systems will demand the use of highly integrated, customized chips in military systems produced in relatively low volumes. Using leading-edge chips in these systems will only be affordable if those chips’ fixed design costs can be reduced dramatically.

The chips Act largely focused on access to advanced fab facilities and production, but absent a game-changing shift, skyrocketing design costs for leading-edge chips remain a silent but critical barrier to exploiting the most advanced technology. DoD’s interest in lowering design costs for military-use chips produced in lower volumes is an idea that, if executed and shared with American industrial partners, would have huge economic spillover benefits. Smaller U.S. chip users, including start‑ups and mid-sized firms, as well as giant tech firms trying to reach smaller niche markets, would greatly benefit.

Currently, a new leading-edge application chip can cost $1 billion to design, verify, and test, and that cost continues to soar at each new technology node. If the number of chip design engineers required on a two-year leading-edge chip development project could be reduced from the present level of three or four hundred down to thirty or forty, a vastly increased set of industrial (and defense) applications could make use of cutting-edge chips, reducing system size, energy requirements, and increasing performance.

An effort to apply AI and other machine learning tools to reduce the human software engineering input required for advanced chip design and could have revolutionary economic consequences. DoD—likely through darpa—should, therefore, take the U.S. government lead in organizing and funding a flagship project that incorporates the latest AI technology into chip design, in collaboration with the tech industry and universities. Since DoD is increasingly hampered in inserting the specialized chip designs it needs for advanced systems because of high design costs, lowering these costs would provide a major impetus toward adopting advanced technology and improving U.S. weapons systems at an affordable rate. Since industry faces the same problem, a collaborative effort is in order. Indeed, some of the new chip design data being created by collaborative chips Act–funded design centers and DoD’s Microelectronics Commons, involving university, government, and industry partners, could be a rich source of data to train AI models in the design of chips with reduced human input.

A Unified and Longer-Term R&D Strategy

Congress handed the semiconductor ball, as noted, to Commerce, and not to DoD, through the chips Act.⁶⁴ While Commerce’s fab construction funding is now largely committed, its National Semiconductor Technology Center (NSTC), with $11 billion for semiconductor R&D and scale-up funding, is now just getting underway. Natcast (National Center for Advanced Semiconductor Technology), a nonprofit public-private entity, has been formed to operate the NSTC consortium of companies, universities, and research labs in undertaking the semiconductor research and development mission. Natcast has released a strategic plan,⁶⁵ and has announced two new flagship semiconductor R&D hubs.⁶⁶ Also awarded is an Advanced Packaging Piloting Facility to work on chip packaging and integration technologies.⁶⁷ This NSTC effort has the potential to serve as nucleus for a significant U.S. push in semiconductor R&D.

DoD has a large stake in the success of the NSTC and should take actions to better align its R&D efforts as well as better share information with NSTC and its projects. The combined DoD and NSTC R&D hubs could also be a synergistic source of training data for the application of AI to chip design in a DoD-led chip design initiative.

Two projects are currently moving forward at DoD, using chips Act funding, that are parallel to work initiated by NSTC. They illustrate the need for better integration. DoD’s office of the Undersecretary for Research and Engineering received $2 billion in funding over five years under chips to create a Microelectronics Commons program for a network of industry-university R&D hubs across the country focused on semiconductor sector advances, which were selected in September 2023.⁶⁸ The effort targeted the mid-term (five-year plus range) but not the longer-term (over ten years), and this technology agenda overlaps with that of the NSTC, which received much greater funding.⁶⁹ Since this DoD effort is a mid-term effort, it is not in a position to solve the longer-term need for game-changing next generation technologies; DoD was explicit at the outset that it would not extend the program beyond five years. This is a misguided design limit that will surely obstruct this effort in addressing real defense industrial base needs. The separate but overlapping DoD and Commerce R&D programs require collaboration.

Also overlapping with Commerce-supported efforts are DoD efforts on 3-D heterogeneous integration packaging (technologies that stack multiple chips and interconnect them vertically to improve performance at lower power, using less costly, smaller size chips). On November 20, 2023, darpa announced plans for a new center for “Next Generation Microelectronics Manufacturing” (NGMM) aimed at both research and prototyping. NGMM is funded at $430 million.⁷⁰ DoD later selected a university-industry consortium to lead the center.⁷¹ In parallel, on the same day as the DoD announcement, NIST announced its own National Advanced Packaging Manufacturing Program (napmp) and funded it with $3 billion from the chips Act.⁷² It, too, is embarking on a major packaging and integration initiative with significantly more funding than darpa’s effort.

These four overlapping DoD and Commerce/NIST programs provide good examples of the need for much closer coordination between the two agencies and their initiatives, for the benefit of both agencies, as well as for industry and university research. DoD’s need for more secure chips differentiates it from some of NIST’s industry-oriented approaches, but coordination of the overlapping agendas remains vital to strengthening the defense industrial base.

Since the 1970s, the semiconductor industry has pursued wave after wave of incremental improvements in manufacturing metal-oxide semiconductor (MOS) chips—culminating in today’s complementary MOS (CMOS) chips.⁷³ That era is coming to an end. With chip size nodes reaching 3 nanometers, then 2 nanometers, and approaching 1 nanometer, we are running out of room to improve silicon chip scaling.⁷⁴ We will need different technological alternatives, and the need to implement such post-CMOS technologies may finally arrive within the next decade.⁷⁵ The importance of continuing electronics and computing advances cannot be overstated, for it will have implications in strategic areas like quantum computing and artificial intelligence.⁷⁶

The semiconductor industry needs to pursue three lines of effort for post-CMOS technologies in order to realize continued performance improvements for microelectronics: (1) more efficient architecture and packaging, (2) new models of computation, and (3) new materials and devices.⁷⁷ Many of the potential advances can be implemented when ready and do not depend on continued microelectronics scaling advances. In other words, if such technologies are ready sooner, we don’t have to wait to implement them. This longer-term role is one in which DoD is positioned to lead. Darpa would be the logical leader for a post-CMOS R&D initiative given its historical role, and success, in microelectronics. NSTC may start to satisfy that need over the years, something for which it has chips Act funding, but DoD should participate fully to ensure that its objectives are met, and that a longer-term effort can build on NSTC work.

For DoD, the purpose of having access to the most advanced silicon manufacturing in the United States is to speed the absorption of new technologies—like AI, new photonic devices, and quantum information technology—into the weapons systems it fields. But investment in access to leading-edge semiconductor fabrication must also be accompanied by an even greater attention to investment in the game-changer post-CMOS technologies that can both transform the nature of warfare as well as strengthen the national industrial base. DoD should fully participate in today’s NSTC, but importantly, push to create a new initiative aimed specifically at post-CMOS technology advances.

There are other issues that require serious policy attention,⁷⁸ including workforce education, funding the modernization of DoD platforms to incorporate advanced chips in its systems, reforming DoD’s glacial industrial security regulatory processes (which can delay its access to advanced chips), and coping with threats to the supply chain for legacy chips incorporated into today’s systems.⁷⁹

But the most urgent agenda is clear: dealing with the defense industrial crisis by securing U.S. access to leading-edge chip manufacturing; a leap forward in application of AI to chip design to reduce costs; investment in keeping our place at the future post-CMOS technological frontier; and a coherent national strategy to organize industry, universities, and the government in a partnership to safeguard both national security and economic prosperity.

Beyond CHIPS

Semiconductors became critical to national security over three decades ago and their security importance is now essential. New kinds of warfare—the Ukraine War is providing an initial glimpse—will require DoD to shift from relying on legacy chip systems to advanced chip systems. DoD nurtured the early evolution of the sector but became less involved after the end of the Cold War. Because the federal government refused to engage in a subsidy competition to finance the massive costs of new semiconductor fabs, no new leading-edge logic fabs had been built in the United States for over a decade, and no new leading-edge memory fabs for roughly two decades, before the chips Act.⁸⁰ Congress passed the chips Act in recognition of this major security vulnerability.

But the chips Act is only authorized for five years, expiring in 2027, and it is not at all clear that it will be renewed. Intel’s major capital program to renew the company’s technology position is also facing challenges, including the departure of the CEO who created the program and the arrival of a new one. Maintaining leadership in semiconductors is a long game, and a renewal of financing support for both R&D and future new fab construction will be needed. Additional support for Intel Foundry in both the short- and medium-term horizons has also become a national security issue: there are no real-world alternatives on the table.

Continued financing is not the only need. Major longer-term initiatives backed by DoD are needed to utilize AI to radically reduce the cost of advanced semiconductor designs, and for post-CMOS R&D. Both areas offer technological game-changing opportunities of first-rank importance. DoD also needs to integrate its current R&D and design efforts with programs evolving at the Commerce Department into a single coherent national initiative. Reversing stagnation and eventually recapturing leadership in advanced chips will not be easy or cheap. Yet the implications for U.S. national security of a failing defense industrial base are too profound and disturbing. The time to act is now.

This article originally appeared in American Affairs Volume IX, Number 2 (Summer 2025): 41–68.

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Notes